/*
## @file
#
#  Copyright (c) 2018 Loongson Technology Corporation Limited (www.loongson.cn).
#  All intellectual property rights(Copyright, Patent and Trademark) reserved.
#
#  Any violations of copyright or other intellectual property rights of the Loongson Technology
#  Corporation Limited will be held accountable in accordance with the law,
#  if you (or any of your subsidiaries, corporate affiliates or agents) initiate
#  directly or indirectly any Intellectual Property Assertion or Intellectual Property Litigation:
#  (i) against Loongson Technology Corporation Limited or any of its subsidiaries or corporate affiliates,
#  (ii) against any party if such Intellectual Property Assertion or Intellectual Property Litigation arises
#  in whole or in part from any software, technology, product or service of Loongson Technology Corporation
#  Limited or any of its subsidiaries or corporate affiliates, or (iii) against any party relating to the Software.
#
#  THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR
#  BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION).
#
#
##
*/
#ifndef _MEMCONFIG_H_INCLUDED_
#define _MEMCONFIG_H_INCLUDED_

#define MC_REGS_COUNT 118
#define MC0_INDEX   0x0
#define MC1_INDEX   0x1
#define SLOT0_INDEX   0x0
#define SLOT1_INDEX   0x1

#ifdef LS3A4000
#define MC0_SLOT0_I2C_ADDR 0x0
#if !defined(QUAL_CPU)
#define MC0_SLOT1_I2C_ADDR 0x1
#define MC1_SLOT0_I2C_ADDR 0x2
#define MC1_SLOT1_I2C_ADDR 0x3
#else
#define MC0_SLOT1_I2C_ADDR 0xf
#define MC1_SLOT0_I2C_ADDR 0x1
#define MC1_SLOT1_I2C_ADDR 0xf
#endif
#elif defined(LS3A3000)
#ifndef DUAL_CPU
#define MC0_SLOT0_I2C_ADDR   0x0
#define MC0_SLOT1_I2C_ADDR   0xf
#define MC1_SLOT0_I2C_ADDR   0x1
#define MC1_SLOT1_I2C_ADDR   0xf
#else
#define MC0_SLOT0_I2C_ADDR   0x0
#define MC0_SLOT1_I2C_ADDR   0x1
#define MC1_SLOT0_I2C_ADDR   0x2
#define MC1_SLOT1_I2C_ADDR   0x3
#endif
#endif

#define HT1_MEM_BASE_ADDR               0x90000e0000000000
#define HT1_CONTROLLER_CONF_BASE_ADDR   0x90000efdfb000000
#define HT_CONF_TYPE0_ADDR              0x90000efdfe000000
#define LOONGSON_PCI_IO_BASE            0x900000001fe00000
#define L2XBAR_CONFIG_BASE_ADDR         0x900000003ff00000
#define CORE_CLKSET_BASE                0x900000001fe001b0
#define MEM_HT_CLKSET_BASE              0x900000001fe001c0
#define LS3A4000_I2C0_BASE_ADDR     0x900000001fe00120
#define LS3A4000_I2C1_BASE_ADDR     0x900000001fe00130
#define CPU_WIN_BASE_OFFSET     0x20
#define CHIP_CONFIG_OFFSET      0x180
#define CHIP_SAMPLE_OFFSET      0x190
#define MISC_BASE_ADDR          0x10080000
#define CONFBUS_BASE_ADDR       0x10010000
#define GPIO_BASE_ADDR_OFFSET   0x60000
#define LS7A_MISC_BASE_ADDR     (HT1_MEM_BASE_ADDR | MISC_BASE_ADDR)
#define ENABLE_DDR_CONFIG_SPACE  0x1
#define DISABLE_DDR_CONFIG_SPACE 0x0

#define NODE_OFFSET     44

#define HT1_RECONNECT   1
#define HT1_GEN_CFG     3
#define HT_WIDTH_CTRL_8     (0x00)
#define HT_WIDTH_CTRL_16    (0x11)
#define HT_WIDTH_CTRL_8BIT  (0)
#define HT_WIDTH_CTRL_16BIT (1)

#if defined(LS7A_2WAY_CONNECT) || (HT1_GEN_CFG == 1)
#define HT1_WIDTH_CFG   HT_WIDTH_CTRL_8BIT
#else
#if defined MULTI_CHIP
#define HT1_WIDTH_CFG   HT_WIDTH_CTRL_8BIT
#else
#define HT1_WIDTH_CFG   HT_WIDTH_CTRL_16BIT
#endif
#endif

#define HT_GEN3_FREQ_CTRL_1600M  (9)
#define HT_GEN1_FREQ_CTRL_800M   (5)

#if (HT1_GEN_CFG == 3)
#define HT1_HARD_FREQ_CFG         HT_GEN3_FREQ_CTRL_1600M
#define LS7A_HT1_SOFT_FREQ_CFG    (LS7A_HT_PLL_1600M | (0x1 << 1))
#define LS7A_HT1_SOFT_FREQ_CFG_C  (LS7A_C_HT_PLL_1600M | (0x1 << 1))
#define LS3A_HT1_SOFT_FREQ_CFG    (LS3A_HT_PLL_1600M | (0x1 << 1))
#else
#define HT1_HARD_FREQ_CFG         HT_GEN1_FREQ_CTRL_800M
#define LS7A_HT1_SOFT_FREQ_CFG    (LS7A_HT_PLL_1600M | (0x1 << 1))
#define LS3A_HT1_SOFT_FREQ_CFG    (LS3A_HT_PLL_1600M | (0x1 << 1))
#endif

#define LS7A_HT_PLL_DIV_LO      22
#define LS7A_HT_PLL_DIV_HI      18
#define LS7A_HT_PLL_DIV_REFC    16
#define LS7A_HT_PLL_LOOPC       9
#define LS7A_HT_PLL_DIV_CTRL    5
#define LS7A_HT_PLL_1600M  ((2 << LS7A_HT_PLL_DIV_LO) | (2 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (32*2 << LS7A_HT_PLL_LOOPC) | (8 << LS7A_HT_PLL_DIV_CTRL))
#define LS7A_C_HT_PLL_1600M  ((2 << LS7A_HT_PLL_DIV_LO) | (2 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (32*2 << LS7A_HT_PLL_LOOPC) | (5 << LS7A_HT_PLL_DIV_CTRL))
#define LS7A_C_HT_PLL_2000M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (20*2 << LS7A_HT_PLL_LOOPC) | (3 << LS7A_HT_PLL_DIV_CTRL))
#ifdef LS3A4000
#ifdef BONITO_100M
#define LS3A_HT_PLL_2400M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (3 << LS7A_HT_PLL_DIV_REFC) | (24*3 << LS7A_HT_PLL_LOOPC) | (4 << LS7A_HT_PLL_DIV_CTRL))
#define LS3A_HT_PLL_1600M  ((2 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (3 << LS7A_HT_PLL_DIV_REFC) | (32*3 << LS7A_HT_PLL_LOOPC) | (8 << LS7A_HT_PLL_DIV_CTRL))
#else
#define LS3A_HT_PLL_2400M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (1 << LS7A_HT_PLL_DIV_REFC) | (24*4 << LS7A_HT_PLL_LOOPC) | (8 << LS7A_HT_PLL_DIV_CTRL))
#define LS3A_HT_PLL_1600M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (1 << LS7A_HT_PLL_DIV_REFC) | (32*2 << LS7A_HT_PLL_LOOPC) | (8 << LS7A_HT_PLL_DIV_CTRL))
#endif
#else
#define LS3A_HT_PLL_2400M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (3 << LS7A_HT_PLL_DIV_REFC) | (24*3 << LS7A_HT_PLL_LOOPC) | (4 << LS7A_HT_PLL_DIV_CTRL))
#define LS3A_HT_PLL_1600M  ((2 << LS7A_HT_PLL_DIV_LO) | (2 << LS7A_HT_PLL_DIV_HI) | (3 << LS7A_HT_PLL_DIV_REFC) | (32*3 << LS7A_HT_PLL_LOOPC) | (8 << LS7A_HT_PLL_DIV_CTRL))
#endif
//#define START_ADDR              0x18
//#define START_OFFSET            0
//
//#define DRAM_INIT_ADDR          0x160
//#define DRAM_INIT_OFFSET        24
//
//#define CS_ENABLE_ADDR           0x168
//#define CS_ENABLE_OFFSET         0

//#define DDR_LOOPC  60 //500MHz

#define BYPASS_CORE 0x0
#define BYPASS_NODE 0x0
#define BYPASS_L1   0x0

#define PLL_CHANG_COMMIT 0x1

#define BYPASS_REFIN        (0x1 << 0)

#ifdef LS3A4000
#define CORE_CLKSEL	0xc0
#define CORE_HSEL	0x80
#define MEM_CLKSEL	(0x3 << 8)
#define MEM_HSEL	(0x2 << 8)
#else
#define CORE_CLKSEL     0x1c
#define CORE_HSEL       0x0c
#define MEM_CLKSEL	(0x01f << 5)
#define MEM_HSEL	(0x0f << 5)
#endif

#define PLL_L1_ENA      (0x1 << 2)
#define PLL_MEM_ENA     (0x1 << 1)
#define PLL_MEM_LOCKED (01 << 16)

#define HT_HSEL (0x1 << 15)

#define HT_32bit_TRANS
#define WITH_HT
#define HT_800M
//#define HT_16bit
#define HT_RECONNECT
//#define HT_REG_TRANS
#define HTMEM_ACC
#define RESET_CRC
#define CHECK_HT_PLL_LOCK
#define CHECK_HT_PLL_MODE
#define CHECK_7A_HT_PLL_LOCK
#endif // _MEMCONFIG_H_INCLUDED_
